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datasheet easypoint tm N40P112 navigation module www.austriamicrosystems.com/N40P112 revision 1.1 1 - 34 1 general description easypoint? N40P112 is a miniature joystick module concept based on contact-less, magnetic movement detection. the integrated two- dimensional linear encoder monitors the movement of the magnet incorporated in the knob and provides directly the x and y coordinates via i2c output. an integrated mechanical push button built in the module provides a ?select? function. figure 1. N40P112-xxxxx-h 2 key features xy coordinates direct read with 8-bit resolution 2.7v to 3.6v operating voltage down to 1.7v i/o voltage lateral magnet movement radius up to 1.0mm high-speed i2c interface configurable interrupt output for motion detection push button feature 3 applications the easypoint? N40P112 is ideal for small form-factor manual input devices in battery operated equipment, such as mobile phones, mp3 players, pdas, gps receivers, gaming consoles and analog joystick replacement. 4 benefits high reliability due to magnetic non-contact sensing low power consumption two operating modes - idle mode - low power mode figure 2. typical application diagram c interrupt supply: i/o dc 2.7 ~ 3.6v dc 1.7 ~ 3.6v i2c interface sda scl vdd intn vddp gpio switch 2x 1k~10k N40P112 push button gnd i2c address gnd: 0x40 vddp: 0x41 as5013 two-dimensional magnetic encoder reset/ gpio 100k 100k
easypoint tm N40P112 datasheet - contents www.austriamicrosystems.com/N40P112 revision 1.1 2 - 34 contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 benefits.................................................................................................................... ................................................................. 1 5 pin assignments ............................................................................................................. .......................................................... 4 5.1 pin descriptions.......................................................................................................... .......................................................................... 4 6 absolute maximum ratings .................................................................................................... .................................................. 5 7 electrical characteristics.................................................................................................. ......................................................... 6 7.1 operating conditions...................................................................................................... ...................................................................... 6 7.2 digital io pads dc/ac characteristics..................................................................................... ............................................................ 6 7.3 switch characteristics .................................................................................................... ...................................................................... 7 7.4 mechanical specifications ................................................................................................. ................................................................... 8 7.5 recommended reflow temperature profile.................................................................................... ..................................................... 8 8 using the N40P112 module .................................................................................................... .................................................. 9 8.1 powering up the module.................................................................................................... ................................................................... 9 8.2 registers initialization.................................................................................................. ......................................................................... 9 8.3 c source code example ..................................................................................................... ............................................................... 10 8.3.1 initialization .......................................................................................................... ...................................................................... 10 8.3.2 offset calibration ...................................................................................................... ................................................................. 10 8.3.3 dead zone area.......................................................................................................... ............................................................... 11 8.3.4 interrupt routine ....................................................................................................... ................................................................. 11 9 xy coordinates interpretation............................................................................................... .................................................. 12 9.1 easypoint operating principle............................................................................................. ............................................................... 12 9.1.1 knob displacement and register value relation........................................................................... ........................................... 13 9.2 operation principle ....................................................................................................... ...................................................................... 14 10 i2c interface .............................................................................................................. ............................................................ 15 10.1 interface operation...................................................................................................... ..................................................................... 15 10.2 i2c electrical specification............................................................................................. ................................................................... 16 10.3 i2c timing ............................................................................................................... .......................................................................... 17 10.4 i2c modes ................................................................................................................ ....................................................................... 17 10.4.1 automatic increment of address pointer ................................................................................. ................................................ 18 10.4.2 invalid addresses ...................................................................................................... .............................................................. 18 10.4.3 reading ................................................................................................................ ................................................................... 18 10.4.4 writing................................................................................................................ ...................................................................... 18 10.4.5 high speed mode ........................................................................................................ ............................................................ 21 10.4.6 automatic increment of address pointer ................................................................................. ................................................ 22 10.4.7 invalid addresses ...................................................................................................... .............................................................. 22 10.5 sda, scl input filters ................................................................................................... .................................................................. 22 11 i2c registers .............................................................................................................. ........................................................... 23 11.1 control register 1 (0fh) ................................................................................................. .................................................................. 23 11.2 x register (10h)......................................................................................................... ....................................................................... 25 11.3 y_res_int register (11h) ................................................................................................. .................................................................. 25 11.4 xp register (12h)........................................................................................................ ...................................................................... 25 11.5 xn register (13h)........................................................................................................ ...................................................................... 25
easypoint tm N40P112 datasheet - contents www.austriamicrosystems.com/N40P112 revision 1.1 3 - 34 11.6 yp register (14h)........................................................................................................ ...................................................................... 26 11.7 yn register (15h)........................................................................................................ ...................................................................... 26 11.8 m_ctrl register (2bh).................................................................................................... .................................................................... 26 11.9 j_ctrl register (2ch).................................................................................................... ..................................................................... 27 11.10 t_ctrl register (2dh) ................................................................................................... ................................................................... 27 11.11 control register 2 (2eh) ................................................................................................ ................................................................. 27 11.12 registers table ......................................................................................................... ...................................................................... 28 12 package drawings and markings .............................................................................................. ........................................... 30 13 ordering information....................................................................................................... ...................................................... 33
easypoint tm N40P112 datasheet - pin assignments www.austriamicrosystems.com/N40P112 revision 1.1 4 - 34 5 pin assignments figure 3. N40P112-xxxxx-h schematics 5.1 pin descriptions table 1. pin descriptions connector pin # pin type description 1 power vddp : io power supply for scl, sda, intn, 1.7v ~ 3.6v 2 power vdd : core power supply, 2.7v ~ 3.6v 3 power gnd 4 bi-directional sda : i2c bus data, open drain 5 input scl : i2c bus clock 6 input resetn : reset input, active low 0: gnd reset, all registers return to their reset value 1: vddp normal operation mode 7 open drain intn : interrupt output, open drain: active: low inactive: hi-z 8 output switchn : push button signal output: not pushed: open pushed: gnd 9 input addr : i2c address selection input: 0: gnd 0x40 1: vddp 0x41 sda 1 scl 2 reset 3 int 4 tb0 5 tb1 6 tb2 7 tb3 8 test_coil 9 addr 10 vddp 11 vdd 12 vss 13 modeotp 14 pclk 15 pdio 16 epad 17 u1 as5013 gnd c2 100n vddp c1 100n vdd gnd scl sda addr intn resetn 1 2 3 4 5 6 7 8 9 j1 ep smd 9pin switchn vdd vddp scl sda intn gnd addr resetn 1 2 s1 dome_switch gnd switchn
easypoint tm N40P112 datasheet - absolute maximum ratings www.austriamicrosystems.com/N40P112 revision 1.1 5 - 34 6 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 6 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min max units notes v dd dc supply voltage -0.3 5 v vddp peripheral supply voltage -0.3 5 vdd + 0.3 v scl, sda, resetn, addr v in input pin voltage -0.3 vddp + 0.3 v scl, sda, resetn, addr -3.6 i scr input current (latchup immunity) -100 100 ma norm: jedec 78 esd electrostatic discharge - 2 kv all pins, norm: mil 883 e method 3015 t strg storage temperature -40 85 oc humidity non-condensing 585% degrees of protection ip5x norm: iec 60529
easypoint tm N40P112 datasheet - electrical characteristics www.austriamicrosystems.com/N40P112 revision 1.1 6 - 34 7 electrical characteristics 7.1 operating conditions t amb = -20 to +70oc, vdd = 3.3v 7.2 digital io pads dc/ac characteristics table 3. operating conditions symbol parameter min typ max units notes vdd core supply voltage 2.7 3.6 v vddp peripheral supply voltage 1.7 vdd v input: resetn open drain outputs: scl, sda, intn. external i2c pull up resistor to be connected to vddp. idd s maximal average current consumption on vdd, pulsed peaks = idd f depends on the sampling time ts[ms] 3+3760/ts [ms] a t amb = -20 to +50 oc 10+3760/ts [ms] t amb = 50 to +70 oc idd i current consumption on core supply, idle mode, no readout (ts = infinite) 3 a t amb = -20 to +50 oc 10 t amb = 50 to +70 oc idd f current consumption on core supply, full power mode 10 ma continuous current pin vdd maximum sampling ts = 450s tpua power up time analog 1000 s step on vdd to data_ready tconv conversion time 450 s read x/y coordinate i2c stop condition to data_ready t p, w nominal wakeup time 20 320 ms t amb ambient temperature range -20 +70 oc resolution of xy displacement 8 over 2*dx and 2*dy axis table 4. digital io pads dc/ac characteristics symbol parameter min max units notes inputs: scl, sda v ih high level input voltage 0.7 * vddp v i2c v il low level input voltage 0.3 * vddp v i2c i leak input leakage current 1 a vddp = 3.6v inputs: addr, resetn (jedec76) v ih high level input voltage 0.65 * vddp v jedec v il low level input voltage 0.35 * vddp v jedec i leak input leakage current 1 a vddp = 3.6v outputs: sda v oh high level output voltage open drain leakage current 1a high level output voltage
easypoint tm N40P112 datasheet - electrical characteristics www.austriamicrosystems.com/N40P112 revision 1.1 7 - 34 7.3 switch characteristics v ol1 low level output voltage vss + 0.4 v -6ma; vddp > 2v; fast mode v ol3 vddp * 0.2 v -6ma; vddp 2v; fast mode v ol1 vss + 0.4 v -3ma; vddp > 2v; high speed v ol3 vddp * 0.2 v -3ma; vddp 2v; high speed c l capacitive load 400 pf standard mode ( 100 khz ) 400 pf fast mode ( 400 khz ) 100 pf high speed mode ( 3.4 mhz ) outputs: intn (jedec76) v oh high level output voltage open drain 1a leakage current high level output voltage v ol low level output voltage vss + 0.2 v -100a vss + 0.45 -2ma c l capacitive load 30 pf standard mode ( 100 khz ) table 5. switch characteristics parameter min max units notes contact resistance of dome switch 500 m norm: eia-364-23 dielectric withstanding voltage 100 vac norm: eia-364-20 insulation resistance 100 m norm: eia-364-21, 100vdc bouncing (on/off) 5 ms rate: 2 times/sec. table 4. digital io pads dc/ac characteristics symbol parameter min max units notes
easypoint tm N40P112 datasheet - electrical characteristics www.austriamicrosystems.com/N40P112 revision 1.1 8 - 34 7.4 mechanical specifications 7.5 recommended reflow temperature profile figure 4. reflow temperature profile table 6. mechanical specifications parameter note number of operating shafts single shaft shaft material lcp housing material lcp & pa46 shell material stainless steel or copper alloy travel (xy operation) 1.00mm (10%) travel (z push operation) 0.22mm (0.05mm) directional operating force (xy direction) N40P112-000x1-h: 0.35n (0.10n) N40P112-000x2-h: 0.55n (0.15n) push operating force (z direction) 1.80n (15%) vibration 10-500-10hz 15 minutes, 12 cycles, 3 axes (total 36 cycles) operating life ? xy direction each direction > 1 million cycles operating life ? push z direction > 1 million cycles shaft strength (xyz direction) > 5.0 kgf free fall dispensing glue 40 drops (2x6 sides + 1x12 edges + 2x8 corners) @ 1.5m drop height to concrete surface, module is assembled to phone mechanics. over force dispensing glue 1.5kgf, > 100k cycles 217oc 170oc 140oc 250 ~ 260c 60 sec. max. 60 ~ 120 sec. pre-heating 10 sec. max. soldering time
easypoint tm N40P112 datasheet - using the N40P112 module www.austriamicrosystems.com/N40P112 revision 1.1 9 - 34 8 using the N40P112 module 8.1 powering up the module the N40P112 module has a power on reset (por) cell to monitor the vdd voltage at startup and reset all the internal registers. after the internal reset is completed, the por cell is disabled in order to save current during normal operation. if vdd drops below 2.7v down to 0.2v, the por cell will not be enabled back, and the registers will not be correctly reseted or can get random values. note: it is highly recommended to control the external resetn signal by applying a low pulse of >100ns once vdd has reached 2.7v and vddp reached 1.7v. figure 5. power-up sequence 8.2 registers initialization after power up, the following sequence must be performed: 1. vdd and vddp power up, and reached their nominal values (vdd>2.7v, vddp>1.7v). 2. initialization: a. resetn pulse low durin g >100ns, then resetn high b. loop check register [0fh] until the value f0h or f1h is present (reset finished, registers to default values) c. write value 0dh into register [2dh] configure t_ctrl scaling factor for 1.0mm knob displacement 3. perform an offset calibration (x and y coordinate compensation for zero position) 4. configure the dead zone area for wake-up function (if needed) 5. configure the wanted power mode and int function into register [0fh] (idle mode / low power mode with timebase configuratio n, int for wake-up or coordinates ready) 6. x y coordinates are ready to be read. external resetn pin, and without power on reset (por) 0v 2.7v 0 vddp (>1.7v) vdd resetn >100ns >1000us internal reset completed power on reset (por) only 0v 0.2v vdd >1000us internal reset completed power up phase vdd @ t=0 between 0v and 0.2v 2.7v power up phase vdd @ t=0 between 0v and 2.7v
easypoint tm N40P112 datasheet - using the N40P112 module www.austriamicrosystems.com/N40P112 revision 1.1 10 - 34 8.3 c source code example 8.3.1 initialization void easypoint_init (void) { unsigned char reset_status = 0; resetn = 0;delay_ms(1);// resetn pulse after power up resetn = 1; delay_ms(1); while (reset_status != 0xf0)// check the reset has been done { reset_status = i2c_read8(0x40, 0x0f) & 0xfe; } i2c_write8(0x40, 0x2d, 0x0d); // scaling factor for n40 (1.0mm knob travel) } 8.3.2 offset calibration void offset_calibrate (void) { char i; int x_cal=0, y_cal=0; ea = 0;// disable the mcu interrupts i2c_write8(0x40, 0x0f, 0x00);// low power mode 20ms delay_ms(1); i2c_read8(0x40, 0x11); // flush an unused y_reg to reset the interrupt for (i=0; i<16; i++)// read 16 times the coordinates and then average { while (intn);// wait until next interrupt (new coordinates) x_cal += (signed char) i2c_read8(0x40, 0x10); // read x position y_cal += (signed char) i2c_read8(0x40, 0x11); // read y position } // offset_x and offset_y are global variables, used for each coordinate readout in the interrupt routine offset_x = -(x_cal>>4); // average x: divide by 16 offset_y = -(y_cal>>4); // average y: divide by 16 ea = 1; // enable the mcu interrupts }
easypoint tm N40P112 datasheet - using the N40P112 module www.austriamicrosystems.com/N40P112 revision 1.1 11 - 34 8.3.3 dead zone area the dead zone area is set around the zero position of the module. the zero position is known after the offset calibration. the dead zone area is a square with a width of 2*center_threshold, around the calibrated zero position. void interrupt_calibrate (center_threshold) { ea = 0; // disable the mcu interrupts i2c_write8(0x40, 0x12, center_threshold - offset_x ); // xp register i2c_write8(0x40, 0x13, -center_threshold - offset_x); // xn register i2c_write8(0x40, 0x14, center_threshold - offset_y); // yp register i2c_write8(0x40, 0x15, -center_threshold - offset_y); // yn register ea = 1; // enable the mcu interrupts } 8.3.4 interrupt routine void easypoint_interrupt (void) interrupt 0 { int x_temp, y_temp; ea=0;// disable mcu interrupts /* optional: if the module is in a slow power mode (e.g. wakeup mode int_function=1 with 320ms rate), configure to a higher rate with intn for new coordinates ready (e.g. int_function = 0 with 20ms rate) */ x_reg = i2c_read8(0x40, 0x10); // read x position y_reg = i2c_read8(0x40, 0x11); // read y position with interrupt reset // add the x and y offset for correct recentering x_temp = x_reg + offset_x; y_temp = y_reg + offset_y; /* optional: if x_temp and y_temp are near the center since a few interrupts, meaning the knob has been released, the module can be put back in a slow power mode (e.g. wakeup mode int_function=1 with 320ms rate) */ ea = 1; // enable the mcu interrupts }
easypoint tm N40P112 datasheet - xy coordinates interpretation www.austriamicrosystems.com/N40P112 revision 1.1 12 - 34 9 xy coordinates interpretation 9.1 easypoint operating principle figure 6. mechanical to xy register interpretation in the following example, the interrupt threshold values xp, xn, yp, yn (see i2c registers on page 23) have been set by the user to xp=10, xn = -10, yp = 10, yn = -10. the four registers are programmable independently for the four directions. when int_function (reg 0fh [2]) = 1, if the knob?s coordinates remains in the area delimited by xp xn yp yn, intn interrupt out put remains high (not active). once the knob moves over this limit, intn goes low (active). for example, this feature can wake up a microcontrol ler from sleep mode. note: due to the mechanical tolerance, the coordinates read on x and y_res_int output registers can show a small offset on both direc tions. to avoid this offset, a calibration function should be implemented in the microcontroller, for example at power up of the syste m. the values x and y_res_int represented in this datasheet are compensated values. for further information, please see chapters 8.2 and 8.3 or refer to the austriamicrosystems N40P112 encoder application notes: http://www.austriamicrosystems.com/eng/products/magnetic-encoders/easypoint-joystick-encoder/as5013 knob on position 1. the knob is released and on its initial position (0,0). the easypoint module is configured with int_function (reg 0fh [2]) = 1. x_reg and y_reg register values are (0,0), and the interrupt is not active. x = 0mm x register = 0 y = 0mm y register = 0 xn = -10 yn = -10 xp = 10 yp = 10 x_reg > xn int = 1 (not active) x = 0.5mm x register = -63 y = 0mm y register = 0 xn = -10 yn = -10 xp = 10 yp = 10 x_reg < xn int = 0 (active) x = 1.0mm x register = -128 y = 0mm y register = 0 xn = -10 yn = -10 xp = 10 yp = 10 x_reg < xn int = 0 (active) 11 x y xn xp yp yn 1 . 0m m connector side connector side connector side 1 2 3 xn xp yp yn xn xp yp yn
easypoint tm N40P112 datasheet - xy coordinates interpretation www.austriamicrosystems.com/N40P112 revision 1.1 13 - 34 knob on position 2. the center of the magnet has been moved upon the horizontal wakeup threshold xp. the easypoint module sets intn low (active). a t this point, the microcontroller can configure the module with int_function (reg 0fh [2]) = 0 and change the low power timebase reg 0 fh [6:4] for a faster reaction time. in this interrupt mode, the interrupt output goes low (active) each time a new x and y value is ready to be read by the microcontroller. the interrupt is reseted high (not active) once the register y_res_int has been read (see i2c registers on page 23) . knob on position 3. the magnet has been moved to the maximum distance from the center (+1.0mm). the maximum x value is -128 decimal. 9.1.1 knob displacement and register value relation figure 7 shows the relation between the x register value and the physical x coordinate of the central knob (1.0mm horizontal displacem ent, 0.0mm is the center of the module, when the knob is released). the y axis measurements are the same as the x axis ones. positive x register values are the left side knob movements, positive y register values are the upper side knob movements. those values are in an ideal condition, where the knob takes place over the center position of the N40P112 sensor once released . the zero position may vary between two n40 modules, and an offset must be applied to x and y in order to compensate the x,y coordinates to 0,0 once the knob is released. more information can be found in chapters 8.2 and 8.3 . figure 7. x register / x displacement (y=0m) x - direction -128 -63 0 63 127 -1000 -500 0 500 1000 mechanical position ( m) register x output
easypoint tm N40P112 datasheet - xy coordinates interpretation www.austriamicrosystems.com/N40P112 revision 1.1 14 - 34 9.2 operation principle figure 8. operation principle start-up. after power up and after ap plying a soft reset (reg 0fh [1]) or hardware reset (resetn input, low pulse >100ns), N40P112 enters the start- up state. during this state the internal registers are loaded with their reset values. then the N40P112 will perform one measur ement and switches automatically into the wait state. measure. the hall element data are measured, x/y coordinates are calculated and available in registers 10h and 11h after tconv = 450s m ax. set interrupt. the intn output is set, depending on the interrupt mode configured in the control register reg 0fh [2] and reg 0fh [3] wait. the module is now in waiting status. a new measurement will occur depending on the power mode (reg 0fh [7] idle = 0 or 1) and t he timebase reg 0fh [6:4] por_n | soft_res | resetn tstartup (1000s) measure start-up: reset internal reg set interrupt wait ( idle=0 & timebase_trigger ) | ( idle=1 & read y) tconv (450s)
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 15 - 34 10 i2c interface the N40P112 supports the 2-wire high-speed i2c protocol in device mode, according to the nxp specification um10204. the host mcu (master) has to initiate the data transfers. the 7-bit device address of the N40P112 depends on the state at the p in addr. addr = 0 slave address =?1000 000? (40h) addr = 1 slave address =?1000 001? (41h) for other i2c addresses, please contact austriamicrosystems . supported modes (slave mode): random/sequential read byte/page write standard mode : 0 to 100 khz clock frequency fast mode : 0 to 400 khz clock frequency high speed : 0 to 3.4 mhz clock frequency the sda signal is bidirectional and is used to read and write the serial data. the scl signal is the clock generated by the hos t mcu, to synchronize the sda data in read and write mode. the maximum i2c clock frequency is 3.4mhz, data are triggered on the rising ed ge of scl. 10.1 interface operation figure 9. i2c timing diagram for fs-mode figure 10. timing diagram for hs-mode sda scl start stop t buf t low t r t hd.sta t high t f t su.dat t su.sta t hd.sta t su.sto repeated start t hd.dat
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 16 - 34 10.2 i2c electrical specification standard-mode, fast-mode, high speed-mode symbol parameter condition min max unit v il low-level input voltage -0.5 0.3vddp v v ih high-level input voltage 0.7vddp vddp + 0.5 1 1. maximum v ih = vddpmax +0.5v or 5.5v, which ever is lower. v v hys hysteresis of schmitt trigger inputs vddp < 2v 0.1vddp - v v ol low-level output voltage (open-drain or open-collector) at 3ma sink current vddp < 2v - 0.2vddp v i cs pull-up current of sclh current source sclh output levels between 0.3vddp and 0.7vddp 312ma t sp pulse width of spikes that must be suppressed by the input filter -10ns i i input current at each i/o pin input voltage between 0.1vddp and 0.9vddp -10a c b total capacitive load for each bus line -400pf c i/o i/o capacitance (sda, scl) 2 2. for capacitive bus loads between 100pf and 400pf, the timing parameters must be linearly interpolated. -10pf
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 17 - 34 10.3 i2c timing 10.4 i2c modes the N40P112 supports the i2c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device recei ving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred t o as slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions must control the bus. the N40P112 operates as a slave on the i2c bus. connections to the bus are made through the open-drain i/o lines sda and t he input scl. clock stretching is not included. symbol parameter condition fs-mode hs-mode c b =100pf hs-mode c b =400pf 1 1. for bus line loads cb between 100 and 400 pf, the timing parameters must be linearly interpolated. unit min max min max min max f sclk scl clock frequency - 400 - 3400 - 1700 khz t buf bus free time; time between stop and start condition 500 - 500 - 500 - ns t hd;sta hold time; (repeated) start condition 2 2. after this time the first clock is generated. 600 - 160 - 160 - ns t low low period of scl clock 1300 - 160 - 320 - ns t high high period of scl clock 600 - 60 - 120 - ns t su;sta setup time for a repeated start condition 600 - 160 - 160 - ns t hd;dat data hold time 3 3. a device must internally provide a minimum hold time (300ns for fast-mode, 80ns / max 150ns for high-speed mode) for the sda signal (referred to the v ihmin of the scl) to bridge the undefined region of the falling edge of scl. 0 900 0 70 0 150 ns t su;dat data setup time 4 4. a fast-mode device can be used in standard-mode system, but the requirement t su;dat = 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the s cl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250ns before the scl line is released. 100 - 10 - 10 - ns t rcl rise time of sclh signal external pull-up source of 3ma - - 10 40 20 80 ns t rcl1 rise time of sclh signal after repeated start condition and after an acknowledge bit external pull-up source of 3ma - - 10 80 20 160 ns t r rise time of sda and scl signals 20+0.1c b 120 - - - - ns t f fall time of sda and scl signals 20+0.1c b 120 - - - - ns t su;sto setup time for stop condition 600 - 160 - 160 - ns v nl noise margin at low level for each connected device (including hysteresis) 0.1vddp - 0.1vddp - 0.1vddp - v v nh noise margin at high level 0.2vddp - 0.2vddp - 0.2vddp - v
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 18 - 34 10.4.1 automatic increment of address pointer the N40P112 slave automatically increments the address pointer af ter each byte transferred. the increase of the address pointer is independent from the address being valid or not. 10.4.2 invalid addresses if the user sets the address pointer to an invalid address, the address byte is not acknowledged. nevertheless a read or write cycle is possible. the address pointer is increased after each byte. 10.4.3 reading when reading from a wrong address, the N40P112 slave data returns all zero. the address pointer is increased after each byte. s equential read over the whole address range is possible including address overflow. 10.4.4 writing a write to a wrong address is not acknowledged by the N40P112 slave, although the address pointer is increased. when the addres s pointer points to a valid address again, a successful write accessed is acknowledged. page write over the whole address range is possib le including address overflow. the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the cloc k line is high are interpreted as start or stop signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid. the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferr ed between start and stop conditions are not limited, and are determined by the master device. the information is transferred byte-wise an d each receiver acknowledges with a ninth bit. acknowledge. each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master devic e must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is st able low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a ma ster must signal an end of read access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of th e slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition.
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 19 - 34 figure 11. data read (write pointer, then read) - slave receive and transmit depending upon the state of the r/w bit, two types of data transfer are possible: data transfer from a master transmitter to a slave receiver: the first byte transmitted by the master is the slave address, followed by r/ w = 0. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. if the slave does no t understand the command or data it sends a ?not acknowledge?. data is transferred with the most significant bit (msb) first. data transfer from a slave tr ansmitter to a master receiver: the master transmits the first byte (the slave address). the slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit af ter all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master devi ce generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with the most significant bit (msb) first. the N40P112 can operate in the following two modes: slave receiver mode (write mode): serial data and clock are received through sda and scl. each byte is followed by an acknowledge bit (or by a not acknowledge depending on the address-pointer poi nting to a valid position). start and stop conditions are reco gnized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address a nd direction bit (see figure 12) . the slave address byte is the first byte received after the start condition. the slave address byte contains the 7-bit N40P112 address, which is stored in the otp memory. the 7-bit slave address is followed by the direction bit (r/w), which, for a write, is 0. after receiving and decoding the slav e address byte the device outputs an acknowledge on the sda. after the N40P112 ac knowledges the slave address + write bit, the master transmits a register address to the N40P112. this sets the address pointer on the N40P112. if the address is a valid readable address the N40P112 an swers by sending an acknowledge. if the address-pointer points to an invali d position a ?not acknowledge? is sent. the master may then t ransmit zero or more bytes of data. in case of the address pointer pointing to an invalid address the received data are not stored. the addr ess pointer will increment after each byte transferred independent from the addr ess being valid. if the address-pointer reaches a valid position again, the N40P112 answers with an acknowledge and stores the data. the master generates a stop condition to terminate the data write. figure 12. data write - slave receiver mode 1 1 9 8 7 6 29 8 7 sda scl start condition stop condition or repeated start condition msb r/w ack lsb ack slave address repeated if more bytes are transferred s 1000000 0 a xxxxxxxx a xxxxxxxx a xxxxxxxx na s ? start a ? acknowledge (ack) data transferred: x+1 bytes + acknowledge p ? stop p xxxxxxxx a
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 20 - 34 slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the N40P112 while the ser ial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. the slave address byte is the f irst byte received after the master generates a start condition. the slave address byte contains the 7-bit N40P112 address. the default a ddress is 80h. the 7-bit slave address is followed by the direction bit (r/w), which, for a read, is 1. after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. the N40P112 then begins to transmit data starting with the register add ress pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode the first ad dress that is read is the last one stored in the register pointer. the N40P112 must receive a ?not acknowledge? to end a read. figure 13. data read (from current pointer location) - slave transmitter mode figure 14. data read (from new pointer location) - slave transmitter mode s 1000000 1 a xxxxxxxx a xxxxxxxx a xxxxxxxx na s ? start a ? acknowledge (ack) data transferred: x+1 bytes + acknowledge na ? not acknowledge (nack) note: last data byte is followed by nack p ? stop p xxxxxxxx a s 1000000 0 a xxxxxxxx a 1000000 1 xxxxxxxx a s ? start sa ? repeated start a ? acknowledge (ack) data transferred: x+1 bytes + acknowledge na ? not acknowledge (nack) note: last data byte is followed by nack p ? stop p xxxxxxxx a sr a xxxxxxxx na
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 21 - 34 10.4.5 high speed mode the N40P112 is capable to work in hs-mode. for switching to hs-mode the master has to send the sequence: start, master code, nack. this sequence is sent in fs-mode. as no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge. after a device receives the master code it has to switch from fs-settings to hs-settings within t su.sta which is 160ns for hs-mode. the device stays in hs-mode as long as it does not receive a stop command. after receiving a stop command it has to switch back form hs-settings to fs-settings, which has to be c ompeted within the minimum bus free time t buf which is 500ns. when switching to hs-mode the slave has to adapt the sdah and sclh input filters according to the spike suppr ession requirement required in hs-mode. in hs-mode spikes up to 10ns, in fs-mode spikes up to 50ns have to be suppressed. adapt the setup and hold times according to the hs-mode requirement. in hs-mode an internal hold time for sda for start/stop detection of 80ns (max. 150ns), in fs-mode an internal hold time of 160ns (max. 250ns) has to be provided. adapt the slope control for sdah output stage. figure 15. data transfer format in hs-mode figure 16. a complete hs-mode transfer s master code na sr slave address r/w data a/ na slave address sr f/s mode hs mode (current source for sclh enabled) p a f/s mode hs mode continues < n bytes + ack >
easypoint tm N40P112 datasheet - i2c interface www.austriamicrosystems.com/N40P112 revision 1.1 22 - 34 10.4.6 automatic increment of address pointer the N40P112 slave automatically increments the address pointer af ter each byte transferred. the increase of the address pointer is independent from the address being valid or not. 10.4.7 invalid addresses if the user sets the address pointer to an invalid address, the address byte is not acknowledged. nevertheless a read or write cycle is possible. the address pointer is increased after each byte. reading: when reading from a wrong address, the N40P112 slave returns all zero. the address pointer is increased after each byte. sequential read over the whole address range is possible including address overflow. writing: a write to a wrong address is not acknowledged by the N40P112 slave, although the address pointer is increased. when the addres s pointer points to a valid address again, a successful write accessed is acknowledged. page write over the whole address range i s possible including address overflow. 10.5 sda, scl input filters input filters for sda and scl inputs are included to suppress noise spikes of less than 50ns. furthermore, the sda line is dela yed by 120ns to provide an internal hold time for start/stop detection to bridge the undefined region of the falling edge of scl. the delay nee ds to be smaller than t hd.sta 260ns. for standard-mode and fast-mode an internal hold time of 300ns is required, which is not covered by the N40P112 slave.
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 23 - 34 11 i2c registers 11.1 control register 1 (0fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 idle time base bit[2] time base bit[1] time base bit[0] int_disable int_function soft_rst data_valid r/w r/w r/w r/w r/w r/w r/w r reset value: 1111 0000 bit bit description 7 0 = low power mode the measurements are triggered with an internal low power oscillator ? the user can select between 8 different timings by setting the low power timebase (control register 1 [6:4]) 1 = idle mode (default) a new measurement cycle is started after the i2c ack bit follow ing the read out of the y-coordinate 11h. the readout rate and thus the power consumption is externally controlled by the host mcu. 6:4 low power time base configure the time base of the automatic wakeup in low power mode (see table 7) . 3 0 = interrupt output intn is enabled (default) 1 = interrupt output intn is disabled and is fixed to ?1? (hi-z) 2 0 = interrupt output intn is active ?0? after each measurement (default): - automatically triggered in low power mode, depending on the time base chosen - 450s after y readout in idle mode the interrupt is cleared after the i2c ack bit following the read out of the y-coordinate 11h. in block read mode, the several other bytes could be transferred before the interrupt is cleared. 1 = interrupt output intn is active ?0? when the movement of the magnet exceeds the dead zone area (see figure 17) . the dead zone area is set by registers xp (reg 12h), xn (reg 13h), yp (reg 14h), yn (reg 15h). the interrupt is cleared after the i2c ack bit following the read out of the y-coordinate 11h, and will be active ?0? at the next measurement if the magnet is still in the detection area. in block read mode, several other bytes can be transferred before the interrupt is cleared. it is recommended to use this mode with the low power mode (idle = 0), in order to wake up automatically a system when the magnet has been moved away from the center. the polling time is the low power time base bit [6:4]. 1 0 = normal mode (default) 1 = reset mode. all the internal registers are loaded with their reset value. the control register 1 is loaded as well with the value 1111 0000, then the soft_rst bit goes back to 0 once the internal reset sequence is finished. 0 0 = conversion of new coordinates ongoing, no valid coordinate is present in the x and y_res_int registers. reading those registers at that moment can give wrong values. 1 = new coordinate values are ready in x and y_res_int registers.
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 24 - 34 figure 17. dead zone representation with int_function=1 note: the values in control register 1, x_register and y_res_int register are frozen when the i2c address pointer is set to 0fh, 10h or 11h. this ensures that the data_valid bit, x and y values are taken at the same time. in order to get updated values from those regi sters, set the address pointer to any other address. table 7. configuration low power time base config_reg1 0fh [6:4] ? t timebase value unit 000b 20 ms 001b 40 ms 010b 80 ms 011b 100 ms 100b 140 ms 101b 200 ms 110b 260 ms 111b (default) 320 ms -128 127 32 64 96 0 -96 -64 -32 -128 32 -32 -64 -96 0 96 64 127 xn xp yp yn x_reg y_reg dead zone area, intn = 1 de tect i on a re a , i ntn = 0 (a ct ive )
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 25 - 34 11.2 x register (10h) 11.3 y_res_int register (11h) 11.4 xp register (12h) 11.5 xn register (13h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x[7] x[6] x[5] x[4] x[3] x[2] x[1] x[0] r r r rrrrr reset value: 0000 0000 bit bit description 7:0 x coordinate, two?s complement format (signed -128 ~ +127). positive x values represent left side knob movements. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y[7] y[6] y[5] y[4] y[3] y[2] y[1] y[0] r r r rrrrr reset value: 0000 0000 bit bit description 7:0 y coordinate, two?s complement format (signed -128~+127). reading this register will reset the intn output to hi-z, after the ack bit of y_res_int register readback. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xp[7] xp[6] xp[5] xp[4] xp[3] xp[2] xp[1] xp[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0000 0101 (5d) bit bit description 7:0 xp range value, two?s complement (signed: -128 ~ +127). determines the left threshold for the activation of intn output (if output enabled), when bit int_function = 1 (see control register 1 (0fh) on page 23) . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xn[7] xn[6] xn[5] xn[4] xn[3] xn[2] xn[1] xn[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 1111 1011 (-5d) bit bit description 7:0 xn range value, two?s complement (signed: -128 ~ +127). determines the right threshold for the activation of intn output (if output enabled), when bit int_function = 1 (see control register 1 (0fh) on page 23) .
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 26 - 34 11.6 yp register (14h) 11.7 yn register (15h) 11.8 m_ctrl register (2bh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yp[7] yp[6] yp[5] yp[4] yp[3] yp[2] yp[1] yp[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0000 0101 (5d) bit bit description 7:0 yp range value, two?s complement (signed: -128 ~ +127). determines the top threshold for the activation of intn output (if output enabled), when bit int_function = 1 (see control register 1 (0fh) on page 23) . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yn[7] yn[6] yn[5] yn[4] yn[3] yn[2] yn[1] yn[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 1111 1011 (-5d) bit bit description 7:0 yn range value, two?s complement (signed: -128 ~ +127). determines the bottom threshold for the activation of intn output (if output enabled), when bit int_function = 1 (see control register 1 (0fh) on page 23) . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m_ctrl[7] m_ctrl[6] m_ctrl[5] m_ctrl[4] m_ctrl[3] m_ctrl[2] m_ctrl[1] m_ctrl[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0000 0000 (00h) bit bit description 7:0 middle hall element control register. the m_ctrl register must be set to 00h (default value) after power up for N40P112 module.
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 27 - 34 11.9 j_ctrl register (2ch) 11.10 t_ctrl register (2dh) 11.11 control register 2 (2eh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 j_ctrl[7] j_ctrl[6] j_ctrl[5] j_ctrl[4] j_ctrl[3] j_ctrl[2] j_ctrl[1] j_ctrl[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0000 0110 (06h) bit bit description 7:0 sector dependent attenuation of the outer hall elements. the j_ctrl register must be set to 06h (default value) after power up for N40P112 module. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t_ctrl[7] t_ctrl[6] t_ctrl[5] t_ctrl[4] t_ctrl[3] t_ctrl[2] t_ctrl[1] t_ctrl[0] r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0000 1001 (09h) bit bit description 7:0 scaling control register. this register controls the scaling factor of the xy coordinates to fit to the 8-bit x and y register (full dynamic range). the t_ctrl register must be set to 0dh after power up for N40P112 module. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test test test test test test inv_spinning test r/w r/w r/w r/w r/w r/w r/w r/w reset value: 1000 0100 bit bit description 7 test bit. must configured ?1?. 6:3 test bit. must configured ?0?. 2 test bit. must configured ?1?. 1 magnet polarity. must be set to ? 0 ? with easypoint modules. 0 test bit. must be ?0?.
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 28 - 34 11.12 registers table the following registers / functions are accessible over the serial i2c interface. table 8. registers register number of bits access address format reset value bit description ic identification id code 8 r 0c 0ch <7:0> 8 bit manufacture id code id version 8 r 0d 0dh <7:4> 8 bit component id version silicon revision 8 r 0e 00h <7:0> 8 bit silicon revision control_register_1 idle 1 r/w 0fh 1b <7> 1 : idle mode 0 : low power mode low_power_timebase 3 r/w 0fh 111b <6:4> low power readout time base register int_disable 1 r/w 0fh 0b <3> disables the interrupt functionality. 1 : interrupt disabled 0 : interrupt enabled int_function 1 r/w 0fh 0b <2> interrupt control register 0 : interrupt goes low with every new calculated x/y coordinates 1 : interrupt pin goes low in when new x/y coordinates are calculated and the magnet has exited the xp, xn, yp, yn threshold values soft_rst 1 r/w 0fh 0b <1> soft reset 0 : normal mode 1 : all registers return to their respective reset value data_valid 1 r 0fh 0b <0> data valid indicator 0 : x/y calculation ongoing 1 : x/y calculation finished, coordinates ready x/y coordinate registers x 8 r 10h two?s comp. 00h <7:0> result x coordinate y_res_int 8 r 11h two?s comp. 00h <7:0> result y coordinate, resets the interrupt flag range settings xp 8 r/w 12h two?s comp. 5h (5 dec) <7:0> wake up threshold @ positive x -direction xn 8 r/w 13h two?s comp. fbh (-5 dec) <7:0> wake up threshold @ negative x -direction yp 8 r/w 14h two?s comp. 5h (5 dec) <7:0> wake up threshold @ positive y -direction yn 8 r/w 15h two?s comp. fbh (-5 dec) <7:0> wake up threshold @ negative y -direction channel voltages (3) c4_neg <11:8> 4 r 16h two?s comp. 00h <3:0> <7:4> voltage @ channel 4, negative current spinning sign extended to 8 bit c4_neg <7:0> 8 r 17h two?s comp. 00h <7:0> voltage @ channel 4, negative current spinning c4_pos <11:8> 4 r 18h two?s comp. 00h <3:0> <7:4> voltage @ channel 4, positive current spinning sign extended to 8 bit c4_pos <7:0> 8 r 19h two?s comp. 00h <7:0> voltage @ channel 4, positive current spinning
easypoint tm N40P112 datasheet - i2c registers www.austriamicrosystems.com/N40P112 revision 1.1 29 - 34 c3_neg <11:8> 4 r 1ah two?s comp. 00h <3:0> <7:4> voltage @ channel 3, negative current spinning sign extended to 8 bit c3_neg <7:0> 8 r 1bh two?s comp. 00h <7:0> voltage @ channel 3, negative current spinning c3_pos <11:8> 4 r 1ch two?s comp. 00h <3:0> <7:4> voltage @ channel 3, positive current spinning sign extended to 8 bit c3_pos <7:0> 8 r 1dh two?s comp. 00h <7:0> voltage @ channel 3, positive current spinning c2_neg <11:8> 4 r 1eh two?s comp. 00h <3:0> <7:4> voltage @ channel 2, negative current spinning sign extended to 8 bit c2_neg <7:0> 8 r 1fh two?s comp. 00h <7:0> voltage @ channel 2, negative current spinning c2_pos <11:8> 4 r 20h two?s comp. 00h <3:0> <7:4> voltage @ channel 2, positive current spinning sign extended to 8 bit c2_pos <7:0> 8 r 21h two?s comp. 00h <7:0> voltage @ channel 2, positive current spinning c1_neg <11:8> 4 r 22h two?s comp. 00h <3:0> <7:4> voltage @ channel 1, negative current spinning sign extended to 8 bit c1_neg <7:0> 8 r 23h two?s comp. 00h <7:0> voltage @ channel 1, negative current spinning c1_pos <11:8> 4 r 24h two?s comp. 00h <3:0> <7:4> voltage @ channel 1, positive current spinning sign extended to 8 bit c1_pos <7:0> 8 r 25h two?s comp. 00h <7:0> voltage @ channel 1, positive current spinning c5_neg <11:8> 4 r 26h two?s comp. 00h <3:0> <7:4> voltage @ channel 5, negative current spinning sign extended to 8 bit c5_neg <7:0> 8 r 27h two?s comp. 00h <7:0> voltage @ channel 5, negative current spinning c5_pos <11:8> 4 r 28h two?s comp. 00h <3:0> <7:4> voltage @ channel 5, positive current spinning sign extended to 8 bit c5_pos <7:0> 8 r 29h two?s comp. 00h <7:0> voltage @ channel 5, positive current spinning control register for the algorithm m_ctrl 8 r/w 2bh 00h <7:0> middle hall element control for N40P112, configure to 00h (default) j_ctrl 8 r/w 2ch 06h <7:0> attenuation of the outer hall elements for N40P112, configure to 06h (default) t_ctrl 8 r/w 2dh 09h <7:0> scaling factor of xy coordinates for N40P112, configure to 0dh control_register_2 test 1 r/w 2eh 1b <7> test only, must be ?1? test 1 r/w 2eh 0b <6> test only, must be ?0? test 1 r/w 2eh 0b <5> test only, must be ?0? test 1 r/w 2eh 0b <4> test only, must be ?0? test 1 r/w 2eh 0b <3> test only, must be ?0? test 1 r/w 2eh 1b <2> test only, must be ?1? inv_spinning 1 r/w 2eh 0b <1> invert the channel voltage. for N40P112, set to ?0? test 1 r/w 2eh 0b <0> test only, must be ?0? table 8. registers register number of bits access address format reset value bit description
easypoint tm N40P112 datasheet - package drawings and markings www.austriamicrosystems.com/N40P112 revision 1.1 30 - 34 12 package drawin gs and markings figure 18. N40P112 dimensions (mm 0.15) figure 19. recommended pcb layout (mm 0.05) d o w n u p r i g h t l e f t ( c o n n e c t o r s i d e )
easypoint tm N40P112 datasheet - package drawings and markings www.austriamicrosystems.com/N40P112 revision 1.1 31 - 34 figure 20. recommended on casing design & mounting note
easypoint tm N40P112 datasheet - revision history www.austriamicrosystems.com/N40P112 revision 1.1 32 - 34 revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 0.8 16 jul, 2010 jlu initial release 1.0 01 dec, 2010 updated applications on page 1 and url in the footer 1.1 16 feb, 2011 updated sections 8.3.1 , 10 , 10.2 , 10.3 , 11.1 , 11.3 , 11.10 , 11.11 , 11.12
easypoint tm N40P112 datasheet - ordering information www.austriamicrosystems.com/N40P112 revision 1.1 33 - 34 13 ordering information the devices are available as the standard products shown in table 9 . note: all products are rohs compliant. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is available at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 9. ordering information ordering code description delivery form N40P112-00001-h 0.35n (0.10n) force tubes N40P112-00011-h 0.35n (0.10n) force tape & reel N40P112-00002-h 0.55n (0.15n) force tubes N40P112-00012-h 0.55n (0.15n) force tape & reel
easypoint tm N40P112 datasheet - copyrights www.austriamicrosystems.com/N40P112 revision 1.1 34 - 34 copyrights copyright ? 1997-2011, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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